A direct exposure system which is one of exposure systems is a system for exposing a printed circuit board to draw a wiring pattern without using any mask. For the exposure, the direct exposure system uses a drawing apparatus by which the wiring pattern designed by a CAD or the like is converted into an exposure pattern matched to the exposure system (this conversion will be referred to as “raster conversion”). The wiring pattern is composed of a set of line segments (vector images) showing the outline of a figure and expressed in a vector format. On the other hand, the exposure pattern is composed of a set of binary (for example, white and black) data (bitmap image data) having a size corresponding to exposure resolution. One binary value is assigned for a to-be-exposed pixel, and the other binary value is assigned for a non-exposed pixel.
In printed circuit boards to be exposed, deformation such as bending, expansion or contraction may occur due to their ambient environment or the like. Each printed circuit board may have its own deformation. In order to improve the yield in manufacturing the printed circuit boards, it is preferable that deformation of each printed circuit board is detected, and an exposure pattern is corrected in accordance with the detected deformation. For the correction of the exposure pattern, it is efficient in view of computational complexity to correct vector images. However, such correction needs to perform the raster conversion in real time. Therefore, it is indispensable to make the raster conversion faster in order to improve the throughput in manufacturing the boards.
The size of the bitmap image data required for exposure has been increasing due to getting a wiring pattern more precise. It is therefore desired to use a high-capacity, low-priced and fast DRAM as a memory for storing the bitmap image data. On the other hand, a wiring pattern is a two-dimensional image and the memory address of a DRAM is one-dimensional. Therefore, random accesses may often occur while the bitmap image data obtained by raster conversion of the wiring pattern are stored into the DRAM. However, since DRAMs are efficient for burst accesses, the accessing efficiency deteriorates when the bitmap image data are stored into the DRAM. To solve this problem, the following method is used by way of example. That is, a part of the bitmap image data stored in the DRAM is read and cached into a cache in burst access. The cache is constituted by an SRAM to which random accesses can be made easily. The raster-converted bitmap image data are read from and written into the cache in random access. Subsequently the cached bitmap image data are written back to the DRAM in a lump. Thus, the efficiency in access to the DRAM can be improved.
For improvement of the efficiency in access to a DRAM, there is a method in which the bitmap image data are compressed and expanded when a part of the bitmap image data is read and written between a cache and the DRAM, so that the size of data read from and written into the DRAM can be reduced (Patent Document 1).
Patent Document 1: JP-A-9-214709 (FIG. 1)
In a drawing apparatus as an exposure system, the yield in manufacturing printed circuit boards is affected by an error of one bit. Therefore, irreversible compression cannot be applied to compression and expansion of bitmap image data between a cache and a DRAM.
For example, run-length encoding (hereinafter referred to as “RLE compression”) is one of reversible methods of compressing bitmap image data. According to such a method, however, the size of compressed data may be larger than the size of its original data when there is a particular relationship between the compression unit size and the pattern of the bitmap image data. The efficiency in access to the DRAM cannot be always improved.